David Terrence Giberti, M.S.

CURRICULUM VITAE & ENGINEERING PORTFOLIO

David Terrence Giberti, M.S.

Staff Design Verification Engineer & Technical Lead — Qualcomm Incorporated

GPU, CPU & Audio DSP Microarchitecture • Standalone C++/DPI-C Reference Validation • Cache, MMU & AMBA CHI/AXI Subsystems

M.S. in Electrical Engineering (San José State University, 3.91 GPA) • M.S. in Computer Science Candidate, Computing Systems (Georgia Institute of Technology) • B.S. in Electrical Engineering (UCLA)

Location: Austin, TX
Electronic Mail: davidgiberti@gmail.com
LinkedIn: linkedin.com/in/davidgiberti
CV Website: www.davidgiberti.com
GitHub Portfolio: github.com/davveeeeeee

I. Academic & Professional Overview

12+ Years Semiconductor Industry Experience • Austin, Texas
Processor Microarchitecture, C++/DPI-C Reference Validation & Memory Subsystems

12+ years across flagship GPU, CPU, AI-accelerator, and Audio DSP silicon combining standalone vector-driven DPI-C++ replay harnesses & C++ reference co-simulation, hardware telemetry & performance-counter verification (ARMv8 SPE, GPU RTU Counters), multi-level cache/MMU & coherent interconnect validation (AMBA CHI/AXI, LSU, TLB), automated RTL-to-Physical-Design PPA flows, and graduate C++ cycle-accurate architectural simulation (SESC).

Staff Design Verification Engineer and Technical Lead at Qualcomm Incorporated in Austin, Texas, with 12+ years of semiconductor industry experience spanning processor microarchitecture verification, C++/DPI-C reference model co-simulation, and post-silicon microprocessor bring-up. Directs, manages, guides, and mentors a team of verification engineers across four Adreno GPU Shader Processor products in the Snapdragon lineup—architecting ground-up SystemVerilog/UVM environments for the Multi-Hop Raytracer / Ray Tracing Tree Traversal Unit (RTTU), Ray Tracing Unit (RTU), Tree Traversal Unit (TTU), Shader L0 Cache, and Matrix Arithmetic Logic Unit (MALU — GPU AI/ML matrix compute processor). Built a standalone vector-driven DPI-C++ replay harness verifying 100% bit-exact equivalence against functional modeling input/output vectors, refactored SystemVerilog/DPI-C++ glue logic linking untimed C++ reference models to cycle-accurate RTL, and engineered mid-simulation reset UVM architectures alongside RTU performance-counter scoreboard updates.

Prior industrial appointments include service as Member of Technical Staff at Advanced Micro Devices (AMD) serving as Technical Lead on x86-64 post-silicon validation, hardware emulation, and System-Level Test (SLT) for EPYC and Ryzen Core Complex (CCX) processors—authoring a custom x86 random assembly generator injected into C++ post-silicon tests and debugging internal pipeline states via an assembly instruction stepper; Audio Design Verification Engineer at Cirrus Logic verifying custom Audio Digital Signal Processors (DSPs) and mixed-signal codecs for flagship consumer mobile and wearable audio devices; CPU Design Verification Engineer at the Samsung Austin R&D Center (SARC | ACL) verifying custom Exynos CPU Load-Store Units (LSU), Page Table-Walkers, and multi-threaded L1 Cache / TLB MMU subsystems; and CPU Design Engineer at Arm Ltd. verifying Cortex-A57, A72, A76, Ares, Zeus, Hera, and Hercules out-of-order CPU frontends, Statistical Profiling Extension (SPE) hardware telemetry, Pointer Authentication (PAC), AMBA CHI/AXI functional coverage, and an automated Jenkins CI/CD RTL-to-Physical-Design synthesis, floorplanning, and place-and-route HTML timing pipeline. Industrial practice is reinforced by graduate coursework in cycle-accurate C++ processor simulation (SESC), out-of-order SystemVerilog hardware design (Mini-Tomasulo RTL), formal deadlock/liveness verification (Synopsys VC-Formal), operating systems concurrency, and AI/ML workloads across Georgia Tech, San José State University, UCLA, UC Santa Cruz, and UT Austin.

Summary of Academic Standing & Cumulative Grade Point Averages (Ordered by Degree Hierarchy)

Online / Part-Time (Expected 2028)
Georgia Institute of Technology
M.S. in Computer Science
Computing Systems Specialization
2012 – 2014
San José State University
M.S. in Electrical Engineering (Logic/Digital & Embedded Systems)
Cumulative GPA: 3.91 / 4.00
Completed 2012
University of California, Los Angeles (UCLA)
B.S. in Electrical Engineering
Concentration: IC Design • Breadth: CS
Expected Completion: December 2026
University of California, Santa Cruz — Silicon Valley Extension
Professional Certificate in Silicon Chip Design & Semiconductor Engineering
Cumulative GPA: 3.93 / 4.00
Completed June 2026 • 9.5 CEUs
The University of Texas at Austin — Texas Executive Education
Post Graduate Program in AI & Machine Learning: Business Applications
Cumulative GPA: 4.28 / 4.33 (A+ Scale; 4.00 / 4.00 Unscaled)

II. Education & Academic Credentials

Ordered by Academic Degree Hierarchy

Georgia Institute of Technology — Atlanta, GA (Online / Part-Time)

Master of Science in Computer Science (Specialization in Computing Systems)

In Progress • Expected Graduation: 2028
Graduate Coursework:
  • CS 6290: High-Performance Computer Architecture
  • CS 6200: Graduate Introduction to Operating Systems
  • CS 8001: Optimization Algorithms in Hardware (OAH)

San José State University — San José, CA

Master of Science in Electrical Engineering (Concentration: Logic/Digital & Embedded Systems Design)

2012 – 2014 • GPA: 3.91 / 4.00
Graduate Coursework:
  • EE 275: Advanced Computer Architectures
  • EE 271: Digital System Design and Synthesis
  • EE 272: SoC Design and Verification with SystemVerilog
  • EE 276: Parallel Computer Architecture
  • EE 287: ASIC CMOS Design
  • EE 224: High-Speed CMOS Circuits
  • CS 286: Quantum Computing
  • EE 221: Principles of Semiconductor Devices I
  • EE 210: Linear System Theory
  • EE 250: Probability and Stochastic Processes

University of California, Los Angeles (UCLA) — Los Angeles, CA

Bachelor of Science in Electrical Engineering (Concentration: Integrated Circuit Design • Breadth: Computer Science)

Completed 2012
Upper-Division Electrical Engineering & Computer Science Coursework:
  • COM SCI M151B: Computer Systems Architecture
  • COM SCI 112: Computer System Modeling Fundamentals
  • COM SCI 180: Introduction to Algorithms and Complexity
  • EL ENGR 115D: Design of Electronic Circuits
  • EL ENGR 115C: Digital Electronic Circuits
  • EL ENGR 115B: Analog Electronic Circuits II
  • EL ENGR 115BL: Analog Electronic Circuits Laboratory
  • EL ENGR 115A: Analog Electronic Circuits I
  • EL ENGR 121B: Principles of Semiconductor Device Design
  • EL ENGR 113: Digital Signal Processing
  • EL ENGR 132A: Communication Systems
  • EL ENGR 141: Principles of Feedback Control
  • EL ENGR 103: Applied Numerical Computing
  • EL ENGR 102: Systems and Signals
  • EL ENGR 101: Engineering Electromagnetics
  • EL ENGR 163A: Introduction to Microwave Circuits

University of California, Santa Cruz — Silicon Valley Extension — Santa Clara, CA

Professional Certificate in Silicon Chip Design and Semiconductor Engineering

Expected Completion: December 2026 • Cumulative GPA: 3.93 / 4.00
Graduate-Level Extension Coursework:
  • VLSI.X415: High-Performance Computer Architecture
  • VLSI.X411: SystemVerilog Assertions and Formal Verification
  • VLSI.X410: System and Functional Verification Using UVM (Universal Verification Methodology)
  • VLSI.X400: Advanced Verification with SystemVerilog OOP Testbench
  • VLSI.X404: Digital Logic Design Using Verilog

The University of Texas at Austin — McCombs School of Business (Texas Executive Education)

Post Graduate Program in Artificial Intelligence and Machine Learning: Business Applications (9.5 CEUs)

Completed June 2026 • GPA: 4.28 / 4.33 (A+ Scale; 4.00 / 4.00 Unscaled)
Completed Graded Curriculum (7 Courses):
Official Credential Verification →
  • Python Foundations (A+)
  • Machine Learning (A+)
  • Advanced Machine Learning (A)
  • Introduction to Neural Networks (A+)
  • Natural Language Processing with Generative AI (A+)
  • Introduction to Computer Vision (A+)
  • Model Deployment (A+)

III. Professional Industry & Academic Experience

Categorized by Industry & Academic Instruction in Reverse-Chronological Order

A. Semiconductor Industry Experience

2013 – Present

Qualcomm Incorporated — Austin, TX

Staff Design Verification Engineer & Team Lead

July 2022 – Present
  • Technical Leadership Across 4 Snapdragon GPU Products: Serve as Technical Lead directing, managing, guiding, and mentoring a team of verification engineers across 4 Adreno GPU Shader Processor products in the Qualcomm Snapdragon lineup.
  • GPU Ray-Tracing, L0 Cache & AI Matrix Subsystems (RTTU, RTU, TTU, L0 Cache & MALU): Architected and built multiple pre-silicon SystemVerilog and UVM microarchitecture verification testbenches from scratch for the Multi-Hop Raytracer / Ray Tracing Tree Traversal Unit (RTTU), Ray Tracing Unit (RTU), Tree Traversal Unit (TTU), Shader L0 Cache, and Matrix Arithmetic Logic Unit (MALU — GPU-integrated AI/ML matrix compute processor).
  • Standalone Vector-Driven DPI-C++ Replay Harness & Reference Co-Simulation: Built a standalone vector-driven DPI-C++ replay harness verifying 100% bit-exact equivalence between functional modeling input/output vectors across the DPI-C++ layer, and architected SystemVerilog wrapper testbenches and DPI-C++ glue logic transforming untimed repository C++ reference model outputs (Ray Intersection, Ray Traversal, Matrix Results) into cycle-accurate transactions checked against live Shader Processor RTL.
  • Mid-Simulation Reset Architecture & Performance-Counter Scoreboard Updates: Engineered mid-simulation reset UVM testbench updates for RTU and TTU subsystems, adapted inherited RTU hardware performance-counter checks and scoreboards to maintain accuracy across testbench enhancements and mid-simulation resets, and drove functional, code, and toggle coverage sign-off with SVA and Python automation.

Advanced Micro Devices (AMD) — Austin, TX

Member of Technical Staff — CPU Post-Silicon Verification Engineer

January 2021 – July 2022
  • Multi-Core EPYC & Ryzen CCX Post-Silicon Bring-Up, Emulation & SLT Lead: Served as Technical Lead on Post-Silicon Design Verification, hardware emulation, and System-Level Manufacturing Test (SLT) of the Core Complex (CCX: CPU Core + Cache/Memory Hierarchy) across x86, x64, MMX, SSE, and AVX architectures for flagship EPYC server and Ryzen client microprocessors.
  • Custom x86 Random Assembly Generator & C++ Post-Silicon Diagnostics: Authored a custom x86 random assembly instruction generator injected into post-silicon C++ diagnostic tests to stress execution pipelines on EPYC and Ryzen silicon and emulators, alongside crafting, debugging, and optimizing bring-up software across CPU hierarchy levels.
  • Silicon Failure Root-Cause Debug via Internal Instruction Stepper: Executed and debugged C++ and x86 assembly post-silicon test suites to verify ISA conformance and expose hardware defects, isolating root-cause silicon and emulation FAILs using an internal EPYC/Ryzen assembly instruction stepper with granular visibility into architectural registers and internal microarchitectural pipeline states.
  • Cross-Functional Debug, Technical Reviews & Mentorship: Led code reviews and technical test-plan reviews, authored test patterns and technical documentation, mentored junior engineers, and partnered across x86 Silicon Design, Physical Design, Pre-Silicon Verification, and Manufacturing teams to resolve silicon and emulation discrepancies.

Cirrus Logic Inc. — Austin, TX

Audio Design Verification Engineer

December 2019 – January 2021
  • Audio DSP & Mixed-Signal Codec Verification Architecture: Personally responsible for design verification architectural plans, technical specifications, and block- and system-level pre-silicon verification for custom Audio Digital Signal Processors (DSPs) and mixed-signal audio codec ICs shipped in flagship consumer mobile and wearable audio products.
  • Primary Block Verification Ownership & Coverage Sign-Off: Served as primary verification owner and subject-matter expert across multiple digital DSP and mixed-signal hardware blocks, driving UVM testbench architecture, constrained-random pattern generation, code and functional coverage closure, and cross-team SoC integration.
  • Mentorship & Milestone Execution: Mentored newly hired engineers and department interns while authoring detailed technical specifications and tracking tapeout milestone progressions.

Samsung Austin R&D Center (SARC | ACL) — Austin, TX

CPU Design Verification Engineer

June 2019 – October 2019
  • Exynos CPU Load-Store Unit & Page Table-Walker Verification: Pre-silicon SystemVerilog and UVM core/uncore engineer responsible for Load-Store Unit (LSU), Page Table-Walker, and Multi-Unit verification environments on custom Samsung Exynos CPUs.
  • Multi-Threaded L1 Cache & TLB MMU Validation: Served as L1 Cache and Translation Lookaside Buffer (TLB) Memory Management Unit (MMU) verification specialist on a multi-threaded CPU implementation, contributing to microarchitectural testbench planning, virtual-to-physical translation verification, and UVM component development.
  • Signature Debug, Coverage & X-Propagation Closure: Executed regression failure debugging, functional and code coverage closure, and X-propagation verification.

Arm Ltd. (ARM Holdings plc) — Austin, TX

CPU Design Engineer

May 2014 – September 2018
  • High-Performance Cortex-A CPU Frontend Verification (A57, A72, A76, Ares, Zeus, Hera, Hercules): Executed core-level pre-silicon verification, microarchitecture bring-up, and release sign-off across Arm Cortex-A57, Cortex-A72, Cortex-A76, Ares, Zeus, Hera, and Hercules out-of-order processors, focusing on Instruction Fetch, Decode, Register Rename, and ALU execution through Commit interfaced with a Load/Store Model.
  • ARMv8.0–v8.4 ISA, Statistical Profiling Extension (SPE) & Pointer Authentication (PAC): Personally owned testbench updates, UVM checkers, instruction scoreboards, SystemVerilog reference checkers, and assembly test patterns verifying ARMv8.0, v8.2, v8.3, and v8.4 architectural features—including the Statistical Profiling Extension (SPE) for hardware latency/event profiling and Pointer Authentication (PAC).
  • Graduate Rotation — Automated Jenkins RTL-to-Physical-Design Synthesis, PnR & HTML Timing Pipeline: Completed a multi-disciplinary rotation across RTL Design, Physical Design, and Design Verification; engineered an automated Jenkins CI/CD system monitoring Git RTL check-ins across individual blocks and the full CPU to execute synthesis, floorplanning, and place-and-route (PnR), automatically generating HTML timing and power reports emailed to RTL designers weekly and upon check-ins to flag broken long paths.
  • AMBA CHI/AXI Functional Coverage, Reset Flop Minimization & Memory Subsystem DV: Performed L0 transaction debugging and authored SystemVerilog functional coverage for AMBA CHI and AXI interconnect protocols, identified minimal resettable flip-flop subsets to prevent pipeline X-propagation, and contributed to the Memory Subsystem Verification Team.

Arm Ltd. (ARM Holdings plc) — Austin, TX

Engineer Intern

May 2013 – August 2013
  • Cortex-A32 Formal Verification, Dead-Code Analysis & Quad-Core SMP Constraints: Performed formal verification and dead-code reachability analysis on the Arm Cortex-A32 processor; analyzed assertion counterexamples and authored formal input assume constraints (without authoring target formal assert properties) to constrain and verify a quad-core SMP configuration paired with three dummy cores.

B. University Teaching & Academic Instruction

2012 – 2014

San José State University — San José, CA

Laboratory Instructor — EE 120: Microprocessor-Based System Design

January 2013 – May 2014
  • x86 Microprocessor Design Laboratory Instruction: Led laboratory courses on x86 microprocessor-based system design; wrote and administered exams and quizzes, delivered weekly lectures, held office hours, and graded student design projects.

San José State University — San José, CA

Instructional Student Assistant — ENGR 100W / 200W: Technical Engineering Writing

August 2013 – May 2014
  • Technical Engineering Writing Instruction: Served as teaching assistant delivering classroom lectures on technical engineering writing and grading undergraduate and graduate research papers.

San José State University — San José, CA

Teaching Assistant / ISA — EE 98 / EE 110: Circuits and Systems

September 2012 – May 2013
  • Circuits & Systems Instruction: Wrote and administered exams and quizzes, delivered weekly lectures, held office hours, and graded coursework for undergraduate electrical engineering students.

Self-Employed — San José, CA

Private English & Technical Writing Tutor

August 2012 – May 2014
  • Academic & Research Writing Instruction: Provided private instruction in advanced writing concepts, technical essays, and academic research papers.

IV. Technical Expertise & Engineering Tools

Simulation, Co-Simulation & EDA

  • Standalone DPI-C++ Vector Replay Harnesses
  • C++ Cycle-Accurate Simulators (SESC — Graduate)
  • Hardware Telemetry & Counters (ARMv8 SPE, GPU RTU Counters)
  • Automated RTL-to-PD Synthesis & PnR Timing Flows (Jenkins CI)
  • Post-Silicon Bring-Up, Hardware Emulation & SLT
  • Internal x86 Assembly Instruction Stepper
  • Synopsys VCS, SIMV, Verdi & Cadence Xcelium / SimVision
  • Verilator, Icarus Verilog & Siemens MTI Questa

Processor & Memory Architecture

  • GPU Ray Tracing & BVH Traversal (RTTU, RTU, TTU)
  • GPU AI/ML Matrix Compute (MALU) & Audio DSPs
  • Multi-Core CCX (EPYC & Ryzen) & Arm Cortex-A Cores
  • Superscalar OoO Pipelines (Fetch, Decode, Rename, ROB, CDB)
  • Branch Prediction (2-Bit Moore FSM, BHT, SESC Predictors)
  • L0/L1/L2 Cache Hierarchies & NXLRU Replacement Policy
  • Load/Store Units (LSU), Page Table-Walkers, TLB MMU & ARMv8 PAC
  • Interconnect Protocols & Coherency (AMBA CHI, AXI, AHB, MESI)

RTL, Co-Simulation & Formal Methods

  • SystemVerilog (IEEE 1800), Verilog-2001 & Synthesizable RTL
  • SystemVerilog DPI-C & C++ Reference Model Glue Logic
  • Universal Verification Methodology (UVM) & SV OOP TBs
  • Mid-Simulation Reset Verification & Scoreboard Architecture
  • Synopsys VC-Formal & Concurrent SVA (Safety, Liveness, Deadlock)
  • Formal Input Constraints, Dead-Code & X-Propagation Flop Analysis
  • Synopsys Design Compiler / Design Vision & Cadence Virtuoso

Software, Concurrency & AI Stack

  • Modern C & C++ (C++17, STL, OOP, Pointers, Simulator Loops)
  • Python (Workflow Automation, Data Analytics & ML Pipelines)
  • Assembly (ARMv8, PAC, ARM Thumb, x86/x64, AVX/SSE, MIPS)
  • POSIX Threads (pthreads), Mutexes, Semaphores & Shared-Mem IPC
  • Distributed Systems (gRPC, Protocol Buffers, Read/Write Locking)
  • Linux (NixOS, RHEL, Pop!_OS), Bash/Zsh/Fish, Vim, Git & Perforce
  • AI/ML Stack (TensorFlow/Keras, Scikit-Learn, XGBoost, LLM/RAG, Docker)

V. Selected Technical Research, Architectural Modeling & Verification Projects

31 Verified Graduate & Undergraduate Engineering Deliverables

VI. Honor Societies, Professional Affiliations & Languages

Honor Societies, Engineering Associations & Leadership

  • The Honor Society of Phi Kappa Phi — Inducted Academic Honor Society Member
  • Institute of Electrical and Electronics Engineers (IEEE) — Professional Member
  • Association for Computing Machinery (ACM) — Professional Member
  • Computer Science Forum — Owner & Founder (Interdisciplinary society advancing knowledge exchange across computer architecture, digital/analog IC design, software engineering, and applied mathematics)

Modern & Classical Languages

  • English: Native / Bilingual Proficiency
  • Hebrew (Modern & Biblical): Limited Working Proficiency
  • Yiddish: Limited Working Proficiency
  • Aramaic: Elementary Proficiency
  • Latin: Elementary Proficiency
  • Japanese: Elementary Proficiency